Design and Implementation of a Reversible Logic Circuit and Its Power Analysis Using Conventional CMOS and Adiabatic Logic

With the advancements in the recent portable electronic gadgets and their prominent applications in various fields, they are expected to be a longer battery life. This requires the semiconductor integrated circuits to be designed with lower power dissipation. The conventional Boolean logic digital ICs consume significant power. This is mainly due to the circuit's irreversible nature (which causes loss of bits of information during its logical operation) and circuit's incomplete switching. This paper deals the above two parameters and confirm that the power reduction can be achieved by designing a circuit in reversible manner and avoiding the incomplete switching by the use of Adiabatic switching. A New 3 × 3 reversible gate is proposed in this paper. It is proved that the proposed New gate can be used as Universal Reversible Gate. This paper also details the implementation of half adder and full adder circuits with the proposed new reversible gate using the CMOS logic and ECRL adiabatic logic and confirm that ECRL adiabatic logic consume less power compare to CMOS logic.